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PCA9691
8-bit A/D and D/A converter
Rev. 02 -- 27 January 2010 Product data sheet
1. General description
The PCA9691 is a single chip, single supply, low power, 8-bit CMOS1 data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins (A0, A1, and A2) are used for programming the hardware address, allowing the use of up to 64 PCA9691 devices connected to the I2C-bus without additional hardware. Address, control and data to and from the PCA9691 are transferred via the serial two-line bidirectional I2C-bus. The functions of the PCA9691 include:
* * * *
Analog input multiplexing On-chip sample and hold 8-bit Analog-to-Digital (A/D) conversion 8-bit Digital-to-Analog (D/A) conversion
The maximum conversion rate is given by the maximum frequency of the I2C-bus.
2. Features
8-bit successive approximation A/D conversion Four analog inputs programmable as single-ended or differential inputs 64 different addresses by three hardware address pins 1 MHz Fast-mode Plus (Fm+) I2C-bus via serial input/output Sampling rate given by I2C-bus frequency Single supply voltage; operating from 2.5 V to 5.5 V Low standby current Analog voltage from VSS to VDD Multiplying Digital-to-Analog Converter (DAC) with one analog output On-chip sample and hold circuit Auto-incremented channel selection
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
3. Ordering information
Table 1. Ordering information Name PCA9691BS PCA9691TS PCA9691T HVQFN16 TSSOP16 SO16 Description plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 7.5 mm Version SOT629-1 SOT403-1 SOT162-1 Type number Package
4. Marking
Table 2. Marking codes Marking code 9691 PCA9691 PCA9691T Type number PCA9691BS PCA9691TS PCA9691T
5. Block diagram
SCL SDA A0 A1 A2 EXT VDD VSS OSC AIN0 AIN1 AIN2 AIN3 SAMPLE AND HOLD ANALOG MULTIPLEXER SAMPLE AND HOLD POWER-ON RESET OSCILLATOR I2C-BUS INTERFACE STATUS REGISTER DAC DATA REGISTER ADC DATA REGISTER
PCA9691
CONTROL LOGIC
COMPARATOR
SUCCESSIVE APPROXIMATION REGISTER AND LOGIC
8
AOUT
DAC
VREF AGND
001aag462
Fig 1.
Block diagram of PCA9691
PCA9691_2
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
6. Pinning information
6.1 Pinning
13 AOUT 12 VREF 11 AGND 10 EXT 9 5 6 7 8 OSC SCL 16 AIN1 15 AIN0 VSS
terminal 1 index area
AIN2 AIN3 A0 A1
1 2
PCA9691BS
3 4
SDA
A2
14 VDD
001aag523
Transparent top view
For mechanical details, see Figure 25.
Fig 2.
Pin configuration for HVQFN16 (PCA9691BS)
AIN0 AIN1 AIN2 AIN3 A0 A1 A2 VSS
1 2 3 4 5 6 7 8
001aag522
16 VDD 15 AOUT 14 VREF 13 AGND 12 EXT 11 OSC 10 SCL 9 SDA
PCA9691TS
Top view. For mechanical details, see Figure 26.
Fig 3.
Pin configuration for TSSOP16 (PCA9691TS)
AIN0 AIN1 AIN2 AIN3 A0 A1 A2 VSS
1 2 3 4 5 6 7 8
013aaa245
16 VDD 15 AOUT 14 VREF 13 AGND 12 EXT 11 OSC 10 SCL 9 SDA
PCA9691T
Top view. For mechanical details, see Figure 27.
Fig 4.
Pin configuration for SO16 (PCA9691T)
PCA9691_2
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
6.2 Pin description
Table 3. Symbol Pin description Pin HVQFN16 TSSOP16 SO16 (PCA9691BS) (PCA9691TS) (PCA9691T) AIN0 AIN1 AIN2 AIN3 A0 A1 A2 VSS SDA SCL OSC 15 16 1 2 3 4 5 6[1] 7 8 9 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 input input input input input input input ground input/output input input/output analog input 0 analog input 1 analog input 2 analog input 3 address input 0 address input 1 address input 2 ground supply (analog and digital) I2C-bus data input and output I2C-bus clock input oscillator signal selection: input, if pin EXT is HIGH output, if pin EXT is LOW EXT 10 12 12 input oscillator selection input: HIGH: external oscillator LOW: internal oscillator AGND VREF AOUT VDD 11 12 13 14
[1]
Type
Description
13 14 15 16
13 14 15 16
ground input output supply
DAC analog ground DAC reference voltage input analog output supply voltage
The die paddle (exposed pad) is connected to VSS and should be electrically isolated.
7. Functional description
7.1 Addressing
Each PCA9691 device in an I2C-bus system is activated by sending a valid address to the device. The address consists of seven programmable bits and one read/write bit. The address must be set according to Table 4. The three input pins (A2, A1, and A0) are used to encode the seven address bits (A[6:0]), where each of the pins can be connected to VDD, VSS, SCL, or SDA. The address is always sent as the first byte after the start condition in the I2C-bus protocol. The last bit of the address byte is the read/write bit which sets the direction of the following data transfer (see Figure 5, Figure 18, and Figure 19).
msb A6 A5 A4 A3 A2 A1 A0
lsb R/W
001aag465
Fig 5.
Address byte
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PCA9691
8-bit A/D and D/A converter
7.1.1 Address map
Table 4. Pin A2 VSS VSS VDD VDD VSS VSS VDD VDD SDA SDA SDA SDA VSS VDD SDA SDA SDA SDA SDA SCL VSS VSS VDD VDD VSS VSS VDD VDD SCL SCL SCL SCL VSS VDD SCL SCL SCL SCL
PCA9691_2
PCA9691 address map Bit A1 VSS VDD VSS VDD SDA SDA SDA SDA VSS VSS VDD VDD SDA SDA VSS VDD SDA SDA SDA SCL VSS VDD VSS VDD SCL SCL SCL SCL VSS VSS VDD VDD SCL SCL VSS VDD SCL SCL A0 SDA SDA SDA SDA VSS VDD VSS VDD VSS VDD VSS VDD SDA SDA SDA SDA VSS VDD SDA SCL SCL SCL SCL SCL VSS VDD VSS VDD VSS VDD VSS VDD SCL SCL SCL SCL VSS VDD A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Address Number
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
PCA9691 address map ...continued Bit A1 SCL SCL VSS VSS VDD VDD VSS VSS VDD VDD SDA SDA SDA SDA SCL SCL VSS VDD VSS VDD SCL SDA SCL SDA SCL SDA A0 SDA SDA VSS VDD VSS VDD VSS VDD VSS VDD SCL SCL VSS VDD VSS VDD SCL SCL SDA SDA SCL SCL SDA SDA SDA SCL A6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h A8h AAh ACh AEh B0h B2h B4h B6h B8h BAh BCh BEh 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Address Number
Table 4. Pin A2 VSS VDD VSS VSS VSS VSS VDD VDD VDD VDD VSS VDD SCL SCL SDA SDA SDA SDA SCL SCL SDA SCL SCL SCL SDA SDA
7.2 Control byte
The second byte sent to a PCA9691 is stored in its control register and is required to control the PCA9691 function. The upper nibble of the control register is used for enabling the analog output, and for programming the analog inputs as single-ended or differential inputs. The lower nibble selects one of the analog input channels defined by the upper nibble (see Figure 6). If the auto-increment flag is set, the channel number is incremented automatically after each A/D conversion. If the auto-increment mode is selected and the internal oscillator is used, the analog output enable flag in the control byte (bit 6) must be set. This allows the internal oscillator to run continuously, thereby preventing conversion errors resulting from oscillator start-up delay. The analog output enable flag can be reset at other times to reduce quiescent power consumption.
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
The selection of a non-existing input channel results in the highest available channel number being allocated. Therefore, if the auto-increment flag is set, the next selected channel is always channel 0. After power-on all bits of the control register are reset to logic 0. The DAC and the oscillator are disabled for power saving. The analog output is switched to a high-impedance state. The most significant bits of both nibbles are reserved for oscillator control. Bit 7 and bit 3 can be set when the interface frequency is fSCL 400 kHz (see Figure 6). Setting these two bits to logic 1 sets the internal frequency to half and the accuracy of the A/D and D/A conversion is 1 LSB as indicated in Table 8 and Table 9. The oscillator output is disabled in normal operation (pin OSC is LOW). Setting bit 7 to logic 0 and bit 3 to logic 1 will enable this output in order to observe the oscillator frequency (divided by 4).
PCA9691_2
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
MSB 0 X X X 0 X X
LSB X CONTROL BYTE A/D CHANNEL NUMBER: 00 channel 0 01 channel 1 10 channel 2 11 channel 3 AUTO-INCREMENT FLAG: active if 1 INTERNAL OSCILLATOR FREQUENCY: 00 full oscillator frequency OSC output disabled 01 full oscillator frequency OSC enabled with 1/4 frequency 10 reserved 11 1/2 oscillator frequency OSC output disabled ANALOG INPUT PROGRAMMING: 00 four single-ended inputs AIN0 channel 0 AIN1 channel 1 AIN2 channel 2 AIN3 channel 3 01 three differential inputs AIN0 channel 0
AIN1
channel 1
AIN2 AIN3
channel 2
10 single-ended and differential mixed AIN0 channel 0 AIN1 channel 1 channel 2 AIN3 11 two differential inputs AIN0 channel 0 AIN1 AIN2 AIN3 ANALOG OUTPUT ENABLE FLAG: analog output active if 1 001aag466 channel 1 AIN2
Fig 6.
Control byte
7.3 D/A conversion
The third byte sent to a PCA9691 is stored in the DAC data register and is converted to the corresponding analog voltage using the on-chip DAC. This DAC consists of a resistor divider chain connected to the external reference voltage (pin VREF) with 256 taps and selection switches. The tap-decoder switches one of these taps to the DAC output line (see Figure 7). The analog output voltage is buffered by an auto-zeroed unity gain amplifier. Setting the analog output enable flag of the control register switches this buffer amplifier on or off. In the active state the output voltage is held until a further data byte is sent.
PCA9691_2
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
In order to release the DAC for a successive approximation A/D conversion cycle, the unity gain amplifier is equipped with a sample and hold circuit. This circuit holds the output voltage while executing the A/D conversion. The formula for the output voltage supplied to the analog output pin AOUT is shown in Figure 8. The waveforms of a D/A conversion sequence are shown in Figure 9. With the rising edge of the 8th clock bit the DAC register is filled with a new value D7 to D0. After some delay the voltage at the analog output starts to change from the previous value to the new value. This delay is random but stays within the following limits:
* Minimum 8Tosc from the rising edge of the 8th bit * Maximum 18Tosc from the rising edge of the acknowledge bit (9th bit)
Where Tosc is the oscillator period (oscillator frequency is given in Table 6). Remark: When AOUT starts changing, the DAC settling time ts(DAC) (specified in Table 8), is required for AOUT to reach a new accurate value.
PCA9691
VREF
R256
DAC out
SAMPLE AND HOLD
unity gain amplifier AOUT
FF
R255
D7 D6
R3
TAP DECODER 02
R2
01
R1
D0
AGND 00
001aag467
Fig 7.
DAC resistor divider chain
PCA9691_2
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
MSB D7 VAOUT VDD VVREF VAOUT = VAGND + D6 D5 D4 D3 D2 D1
LSB D0 DAC data register
VVREF - VAGND 7 Di x 2i 256 i=0
VAGND VSS 00 01 02 03 04 FE FF DAC (hex)
001aag468
Fig 8.
DAC data and DC conversion characteristics
protocol
S
ADDRESS
0
A
CONTROL BYTE
A
DATA BYTE 1
A
DATA BYTE 2
A
SCL
1
2
8
9
1
8
9
1
8
9
1
8
9
SDA VAOUT td ts(DAC) td ts(DAC)
high-impedance state of previous value held in DAC register
previous value held in DAC register
value of data byte 1
time
001aag469
Fig 9.
D/A conversion sequence
7.3.1 Worst case example
An example of the worst case is shown in Figure 10. The delay time can have a value between 8Tosc and 18Tosc. When the I2C-bus is driven at 1 MHz (full speed) then the DAC is operating at a rate of 9 s. The previous AOUT value is valid at least until the rising edge of the acknowledge bit (8Tosc 1.23 s). The latest start time of the new value is 5.6 s from the rising edge of the acknowledge bit: (18Tosc 5.6 s) so AOUT is stable after ts(DAC) 2.4 s.
PCA9691_2
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
The new AOUT value is valid, at the latest, after 8.0 s so before the rising edge of the 8th bit of the next transferred byte. Therefore, at the full speed of the I2C-bus, the analog output is valid under all circumstances between the rising edges of the 8th bit and the acknowledge bit.
SCL
6
7
8 > 8Tosc
A
1
2 3 < 18Tosc
4
5
6 ts(DAC)
7
8 valid
A
1
2
VAOUT
001aag470
Fig 10.
D/A conversion sequence, example of worst case
7.4 A/D conversion
The A/D Converter (ADC) makes use of the successive approximation conversion technique. The on-chip DAC and a high-gain comparator are used temporarily during an A/D conversion cycle. An A/D conversion cycle is always started after sending a valid read mode address to a PCA9691. The A/D conversion cycle is triggered at the trailing edge of the acknowledge clock pulse and is executed while transmitting the result of the previous conversion (see Figure 11).
protocol
S
ADDRESS
1
A
DATA BYTE 0
A
DATA BYTE 1
A
DATA BYTE 2
A
SCL 1 2 8 9 1 9 1 9 1
SDA
sampling byte 1
sampling byte 2
sampling byte 3
conversion of byte 1 transmission of previously converted byte
conversion of byte 2 transmission of byte 1
conversion of byte 3 transmission of byte 2
mbl829
Fig 11. A/D conversion sequence
Once a conversion cycle is triggered, an input voltage sample of the selected channel is stored on the chip and is converted to the corresponding 8-bit binary code. Samples picked up from differential inputs are converted to an 8-bit two's complement code (see Figure 12 and Figure 13). The conversion result is stored in the ADC data register and awaits transmission. If the auto-increment flag is set the next channel is selected.
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
The first byte transmitted in a read cycle contains the conversion result code of the previous read cycle. After a Power-On Reset (POR) condition the first byte read is 80h. The protocol of an I2C-bus read cycle is shown in Figure 19. The actual speed of the I2C-bus provides the maximum A/D conversion rate.
ADC (hex)
FF FE VVREF - VAGND 256
VLSB =
04 03 02 01 00 0 1 2 3 4 254 255 VAIN - VAGND VLSB
001aah587
Fig 12. A/D conversion characteristics of single-ended inputs
PCA9691_2
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
ADC (hex)
7F 7E
02 01 00 -128 -127 -2 -1 0 FF FE VVREF - VAGND 256 81 80 1 2 126 127 VAIN+ - VAIN- VLSB
VLSB =
001aah588
Fig 13. A/D conversion characteristics of differential inputs
7.5 Reference voltage
For the D/A and A/D conversion either a stable external voltage reference or the supply voltage has to be applied to the resistor divider chain (pins VREF and AGND). Pin AGND has to be connected to the system analog ground and may have a DC off-set with reference to VSS. A low frequency may be applied to pins VREF and AGND. This allows the use of the DAC as a one-quadrant multiplier (see Figure 12 and Figure 24). The ADC may also be used as a one- or two-quadrant analog divider. The analog input voltage is divided by the reference voltage. The result is converted to a binary code. In this application the user has to keep the reference voltage stable during the conversion cycle.
7.6 Oscillator
An on-chip oscillator generates the clock signal required for the A/D conversion cycle and for refreshing the auto-zeroed buffer amplifier. When using this oscillator pin EXT has to be connected to VSS. The oscillator frequency divided by 4 is available at output pin OSC (see Section 7.2). However, in normal operation it is recommended that output pin OSC is disabled. In this case the output pin OSC is LOW. The oscillator starts when a start condition is sent via the I2C-bus interface. If the received address is recognized as valid the oscillator continues to run. If the received address is not recognized the oscillator stops. If a stop condition occurs the oscillator is stopped unless pin AOUT is enabled.
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
It is recommended that if the I2C-bus speed fSCL 400 kHz, you must reduce the oscillator frequency by half (see the definition of the control byte in Figure 6). If pin EXT is connected to VDD the oscillator output OSC is switched to a high-impedance state allowing to feed an external clock signal to the OSC input. The frequency of the external clock must be in the specified range.
7.7 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different IC or modules. The two lines are a Serial DAta Line (SDA) and a Serial Clock Line (SCL). Both lines are connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
7.7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 14).
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 14. Bit transfer
7.7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 15).
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 15. Definition of start and stop condition
PCA9691_2
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
7.7.3 System configuration
A device which sends data to the bus is a transmitter, a device which receives data from the bus is a receiver. The device which initiates and terminates a transfer is the master; and the devices which are addressed by the master are the slaves (see Figure 16).
SDA SCL MASTER TRANSMITTER RECEIVER SLAVE TRANSMITTER RECEIVER MASTER TRANSMITTER RECEIVER
mba605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig 16. System configuration
7.7.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
* A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
* A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
* The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
* A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 17.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 17. Acknowledgement on the I2C-bus
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
7.7.5 I2C-bus protocol
After a start condition a valid hardware address has to be sent to a PCA9691 device. The read/write bit defines the direction of the following single or multiple byte data transfer. For the format and the timing of the start condition (S), the stop condition (P) and the acknowledge bit (A) refer to the I2C-bus characteristics. In the write mode a data transfer is terminated by sending either a stop condition or the start condition of the next data transfer.
acknowledge from PCA9691 S ADDRESS 0 A
acknowledge from PCA9691 A
acknowledge from PCA9691 A P/S
001aag471
CONTROL BYTE
DATA BYTE N = 0 to M data bytes
Fig 18. Bus protocol for write mode, D/A conversion
acknowledge from PCA9691 S ADDRESS 1 A
acknowledge from master A
no acknowledge
DATA BYTE N = 0 to M data bytes
LAST DATA BYTE
1
P
001aag472
Fig 19. Bus protocol for read mode, A/D conversion
8. Internal circuitry
VDD
SCL
SDA
A0
A1
A2
EXT
OSC
VREF
AGND
AIN0
AIN1
AIN2
AIN3
AOUT
VSS
001aah585
Fig 20. Device protection
9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II
PCA9691_2
Parameter supply voltage input voltage input current
Conditions
Min -0.5 -0.5 -
Max +6.5 VDD + 0.5 10
Unit V V mA
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
Table 5. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol IO IDD ISS Ptot Po VESD Ilu Tstg Tamb
[1] [2] [3] [4]
Parameter output current supply current ground supply current total power dissipation output power electrostatic discharge voltage latch-up current storage temperature ambient temperature
Conditions
Min -
Max 20 +50 -50 300 100 1500 200 100 +150 +85
Unit mA mA mA mW mW V V mA C C
HBM MM
[1] [2] [3] [4]
-65 -40
Pass level; Human Body Model (HBM), according to Ref. 5 "JESD22-A114". Pass level; Machine Model (MM), according to Ref. 6 "JESD22-A115". Pass level; latch-up testing according to Ref. 7 "JESD78" at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see Ref. 9 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.
10. Characteristics
10.1 Static characteristics
Table 6. Static characteristic VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Supply VDD IDD supply voltage supply current VI = VSS or VDD; no load standby no bus activity bus activity operating; fSCL = 1 MHz pin AOUT off pin AOUT active VPOR VIL VIH IL Ci IOL
PCA9691_2
Conditions
Min 2.5
Typ 5.0
Max 5.5
Unit V
[1]
1.5 10 500 1400 -
10 100 1400 2500 2.0 0.3VDD +100 550 -
A A A A V V V nA pF mA
power-on reset voltage LOW-level input voltage HIGH-level input voltage leakage current input capacitance LOW-level output current VOL = 0.4 V; VDD = 5 V; CL = 550 pF; fSCL = 1 MHz VI = VSS to VDD
0.8 0 0.7VDD -100 24
Digital inputs: pins SCL, SDA, A0, A1, A2, OSC and EXT
Digital output: pin SDA
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
Table 6. Static characteristic ...continued VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter VVREF VAGND ILI Rref voltage on pin VREF voltage on pin AGND input leakage current reference resistance resistance between pin VREF and pin AGND Conditions VVREF - VAGND 1.6 V VVREF - VAGND 1.6 V Min 1.6 VSS -100 Typ 40 Max VDD VDD - 1.6 +100 Unit V V nA k Reference inputs: pins VREF and AGND
Oscillator: pin OSC fosc(int) fosc(ext) internal oscillator frequency pin EXT is LOW external oscillator frequency pin EXT is HIGH 3.2 3.5 8.0 5.5 MHz MHz
[1]
The power-on reset circuit resets the I2C-bus logic when VDD < VPOR.
640 IDD (A) 480
001aag463
320
160
0 2 3 4 5 VDD (V) 6
Internal oscillator on; analog output disabled; Tamb = 27 C
Fig 21. Operating supply current as a function of supply voltage (typical)
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8-bit A/D and D/A converter
50 ZAOUT () 40
001aag464
50 ZAOUT () 40
001aag474
30
30
20
20
10
10
0 00 02 04 06 08 0A hex input code
0 EB
EF
F3
F7
FB FF hex input code
a. Output impedance near negative power rail (VSS)
b. Output impedance near positive power rail (VDD)
Tamb = 27 C; VDD = 5 V; VVREF = 5 V; VAGND = 0 V, (typical values)
Fig 22. Output impedance of analog output buffer (near power rails)
10.2 Dynamic characteristics
Table 7. I2C-bus characteristics VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 23). Symbol Parameter fSCL tBUF SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock
[2]
Conditions
[1]
Standard mode Min 0 4.7 Max 100 -
Fast mode Min 0 1.3 Max 400 -
Fast-mode Plus Unit Min 0 0.5 Max 1000 kHz s
tHD;STA tSU;STA
4.0 4.7
-
0.6 0.6
-
0.26 0.26
-
s s
tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH
4.0 0 0.1 300 250 4.7 4.0
3.45 -
0.6 0 0.1 75 100 1.3 0.6
0.9 -
0.26 0 0.05 75 50 0.5 0.26
0.45 450 -
s ns s ns ns s s
[3]
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Product data sheet
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8-bit A/D and D/A converter
Table 7. I2C-bus characteristics ...continued VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 23). Symbol Parameter tf tr fall time of both SDA and SCL signals rise time of both SDA and SCL signals spike pulse width Conditions
[4][5][6]
Standard mode Min Max 300 1000
Fast mode Min 20 + 0.1Cb 20 + 0.1Cb Max 300 300
Fast-mode Plus Unit Min Max 120 120 ns ns
[4][5][6]
tw(spike)
[1] [2] [3] [4] [5] [6]
[7]
-
50
-
50
-
50
ns
The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. You must disable the bus time-out feature for DC operation. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for valid SDA (out) data following SCL LOW. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the SCL's falling edge. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA pin and the SDA bus line and between the SCL pin and the SCL bus line without exceeding the maximum tf. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
[7]
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
tSU;STA
tLOW
tHIGH
1 / fSCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
mbd820
Rise and fall times refer to 30 % and 70 %
Fig 23. I2C-bus timing diagram
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
Table 8. D/A characteristics VDD = 5.0 V; VSS = 0 V; VVREF = 5.0 V; VAGND = 0 V; Tamb = -40 C to +85 C; RL = 10 k; CL = 50 pF; unless otherwise specified. Symbol Parameter Analog output VAOUT ILO Accuracy EG EO EL ts(DAC) fc(DAC) sup(n)
[1] [2]
Conditions no resistive load RL = 10 k pin AOUT disabled no resistive load fSCL 400 kHz fSCL > 400 kHz
[1] [1] [2]
Min VSS VSS -100 -
Typ 40
Max VDD 0.9VDD +100 1 20 1.0 1.5 2.4 44 -
Unit V V nA % mV LSB LSB s kHz dB
voltage on pin AOUT output leakage current gain error offset error linearity error DAC settling time DAC conversion frequency noise suppression
f = 100 Hz; Vn(VDD)(p-p) = 100 mV
The linearity error is assured if the internal frequency is changed by setting bit 7 and bit 3 of the control byte to logic 1 (see Figure 6). The time from the start of AOUT to a change of 12 LSB full scale (see Section 7.3).
Table 9. A/D characteristics VDD = 5.0 V; VSS = 0 V; VVREF = 5.0 V; VAGND = 0 V; Tamb = -40 C to +85 C; RL = 10 k; CL = 50 pF; unless otherwise specified. Symbol VAIN ILI Ci(a) Ci(dif) Vi(se) Vi(dif) Accuracy EG EO EL CMRR sup(n) tc(ADC) fc(ADC) gain error offset error linearity error common-mode rejection ratio noise suppression ADC conversion time ADC conversion frequency fSCL = 1 MHz f = 100 Hz; Vn(VDD)(p-p) = 100 mV fSCL 400 kHz fSCL > 400 kHz
[1] [1]
Parameter voltage on pin AIN input leakage current analog input capacitance differential input capacitance single-ended input voltage differential input voltage
Conditions pins AIN0 to AIN3
Min VSS -100 -
Typ 10 10 -
Max VDD +100 VVREF +0.5VFSR
Unit V nA pF pF V V
Analog inputs
measuring range measuring range: VFSR = VVREF - VAGND fSCL 400 kHz fSCL > 400 kHz
VAGND -0.5VFSR
-
40 40 -
1 3 20 1.0 2.0 8.5 111
% % mV LSB LSB dB dB s kHz
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Product data sheet
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NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
[1]
The linearity error is assured if the internal frequency is changed by setting bit 7 and bit 3 of the control byte to logic 1 (see Figure 6).
11. Application information
Inputs must be connected to VSS or VDD when not in use. Analog inputs may also be connected to pins AGND or VREF. In order to prevent excessive ground and supply noise and to minimize crosstalk of the digital-to-analog signal paths the printed-circuit board layout must be designed very carefully. Noisy digital circuits and ground loops must be avoided on the supply lines common to the PCA9691 device. Decoupling capacitors (> 10 F) are recommended for power supply and reference voltage inputs. During data transfer the first bit written out is the MSB and the last bit is the LSB.
VDD VDD
V0
VDD
AIN0 AIN1 AIN2 VDD
VDD
AOUT VREF AGND
VOUT
AIN3 PCA9691 EXT A0 A1
OSC SCL VSS SDA
A2
VDD AIN0 AIN1
V0 V1
VDD
AOUT VREF AGND
VOUT
AIN2 VDD
V2
AIN3 PCA9691 EXT A0 A1 A2 VSS OSC SCL SDA
VDD analog ground digital ground MASTER TRANSMITTER I2C-bus
001aag473
Fig 24. Application diagram
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Product data sheet
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8-bit A/D and D/A converter
12. Package outline
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
D
B
A
terminal 1 index area E
A
A1 c
detail X
e1
1/2
C e b 8 vMCAB wMC y1 C y
e 5 L
4
9 e
Eh
1/2
e2 e
1 12
terminal 1 index area
16 Dh 0
13 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.38 0.23 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.65 e1 1.95 e2 1.95 L 0.75 0.50 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT629-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 25. Package outline SOT629-1 (HVQFN16) of PCA9691BS
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Product data sheet
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PCA9691
8-bit A/D and D/A converter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 26. Package outline SOT403-1 (TSSOP16) of PCA9691TS
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PCA9691
8-bit A/D and D/A converter
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
o
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 27. Package outline SOT162-1 (SO16) of PCA9691T
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PCA9691
8-bit A/D and D/A converter
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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8-bit A/D and D/A converter
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2 000 260 250 245 > 2 000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28.
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Product data sheet
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8-bit A/D and D/A converter
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 28. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 12. Acronym CMOS DAC DC HBM I2C IC LSB MM MSB MSL PCB POR SCL SDA SMD Abbreviations Description Complementary Metal Oxide Semiconductor Digital-to-Analog Converter Direct Current Human Body Model Inter-Integrated Circuit bus Integrated Circuit Least Significant Bit Machine Model Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Serial Clock Line Serial DAta line Surface Mount Device
15. References
[1]
PCA9691_2
AN10365 -- Surface mount reflow soldering description
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 -- 27 January 2010
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PCA9691
8-bit A/D and D/A converter IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices NX3-00092 -- NXP store and transport requirements
[2] [3] [4] [5] [6] [7] [8] [9]
[10] SNV-FA-01-02 -- Marking Formats Integrated Circuits [11] UM10204 -- I2C-bus specification and user manual
16. Revision history
Table 13. Revision history Release date 20100127 Data sheet status Product data sheet Product data sheet Change notice Supersedes PCA9691_1 Document ID PCA9691_2 Modifications: PCA9691_1
*
Added new package and product type PCA9691T
20080408
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8-bit A/D and D/A converter
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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8-bit A/D and D/A converter
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.3 7.3.1 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 8 9 10 10.1 10.2 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address map . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 D/A conversion . . . . . . . . . . . . . . . . . . . . . . . . . 8 Worst case example . . . . . . . . . . . . . . . . . . . . 10 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . 11 Reference voltage. . . . . . . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics of the I2C-bus. . . . . . . . . . . . . 14 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 START and STOP conditions . . . . . . . . . . . . . 14 System configuration . . . . . . . . . . . . . . . . . . . 15 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 16 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics . . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 19 Application information. . . . . . . . . . . . . . . . . . 22 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering of SMD packages . . . . . . . . . . . . . . 26 Introduction to soldering . . . . . . . . . . . . . . . . . 26 Wave and reflow soldering . . . . . . . . . . . . . . . 26 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact information. . . . . . . . . . . . . . . . . . . . . 30 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 January 2010 Document identifier: PCA9691_2

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